A New Class of Asynchronous Analog-to-Digital Converters

This work is a contribution to a drastic change in standard signal processing chains: Analog-to-Digital Converters (ADCs), digital processing circuits, Digital-to-Analog Converters (DACs)… Integrated Smart Devices and Communicating Objects are the important applications targeted by this study. The main objective is to reduce their power consumption by one or two orders of magnitude, by completely rethinking their architectures and the associated signal processing theory. In this context, we present a new class of ADCs, based on an irregular sampling of the input analog signal to process (level-crossing sampling), and on an asynchronous implementation (without any global clock). Fixed quantization levels are disposed along the input dynamic of the converter, a sample is taken and processed only when the signal crosses one of them. Its amplitude is then perfectly known (it is the one of the corresponding crossed level), and its time instant is quantized according to the resolution of a timer, the purpose of which is only to date the samples. Of course, the occurrences of samples depend on the signal amplitude variations: this sampling scheme removes the conversion of redundant samples or samples without any relevant information when the analog signal is quiet. Therefore, it leads to a compression of the digital samples and a reduction of the activity of the circuit. The principle of this asynchronous A/D conversion is the dual case of Nyquist ADCs where the time instants are perfectly known and where the amplitude of samples is quantized. It leads to a completely different theory concerning the Signal-to-Noise Ratio (SNR) and the analog signal reconstruction. Hence a new design method has been elaborated: given an Effective Number Of Bits (ENOB) and the characteristics of the input analog signal to process (statistical properties and power spectral density), it determines the design parameters of the asynchronous ADC. It is shown that this method leads to a significant reduction in terms of hardware complexity and power consumption. The asynchronous ADC has been designed, in a 0.18µm CMOS technology from STMicroelectronics, for a speech application, according to our design method. A 3-stage, micropipelined architecture, and a 4-phase protocol have been chosen for its implementation. The difference with classical pipelined circuits is that the data path part is here composed of digital and analog blocks (comparators, DAC…). Electrical simulations of the whole converter have been processed to determine its Factor of Merit (FoM). Comparisons with recent publications concerning any architecture (Flash, …